1. Field of the Invention
The present invention relates to a recording-medium operating device and method for data operation such as data-write/data-read to recording media such as optical disks, magneto optical disks and the like used for computers, audio devices, video devices and the like and a method for operating a recording medium. More particularly, it relates to a recording-medium operating device capable of coping with a wide-range data transfer rate using delay circuit with not so large number of stages, a clock signal generating device for the recoding-medium operating device, and a method for generating a clock signal.
2. Description of Related Art
Data operation such as data-write, data-read, and the like to a recoding medium such as an optical disk (simply termed as “disk” hereinafter) is conducted along with clock signals for taking timing. As one of the manners for generating a clock signal, there can be raised external clock system wherein a clock signal is obtained by reproducing a clock mark that has previously been formed on a disk as a phase information mark.
Generation of a clock signal in accordance with external clock system is carried out as follow. Firstly, there will be described a reference clock mark on a disk. As shown in FIG. 10, FCM (Fine Clock Mark) and data regions are alternately arranged on a disk. An FCM herein corresponds to a clock mark. A segment consists of an FCM and a following data region. When laser beam is irradiated to an FCM, reflected laser beam generates a pulse signal. A necessary multiplication is made by a PLL (Phase-Locked Loop) based on the pulse signal, whereby, a reference clock is generated. Data operation for following data regions is carried out along with this reference clock.
In a typical disk operating device, processing for generating the above-mentioned reference clocks and data operation processing to data regions based on reference clocks are separately conducted by respective processing systems. Therefore, there is possibility that frequency difference and phase difference between a reference clock and data on a data region occur. Furthermore, individual differences of devices and disks themselves can possibly cause frequency difference or phase difference between a reference clock and data on a data region. Accordingly, it is required to meet timing of data on a data region with a reference clock. For such a reason, a phase of a reference clock is corrected.
Phase correction is conducted with a delay line as shown in FIG. 17. A delay line is consists of a significant number of buffer logics connected in series. Out of delay clocks outputted from respective adjoining buffer logics, a delay signal that has the smallest phase difference with a read signal is selected as a reference clock. A data correction pattern is previously recorded on a head portion of a data region on the disk shown in FIG. 10 and when a data correction pattern is read out, a read signal is obtained. Being sampled with read signals obtained by reference clocks, data Dn−1, Dn, Dn+1, . . . , as shown in FIG. 11, are obtained. Since the sample in FIG. 11 is a case without a phase difference, there is no difference between data Dn and its expected value En. However, in case with a phase difference, the data Dn may not coincide with the expected value En, as shown in FIG. 12. Thereby, it can be judged whether a phase of a read signal meets with a phase of a reference signal (Dn=En) or not meet, and further, ahead the reference signal (Dn>En) or behind the reference signal (Dn<En).
However, the above-mentioned prior art has following problems. That is, number of stages required for a delay line is too large. That is, delay quantity for the entirety of the delay line of FIG. 17 need to be taken longer than one-cycle of a reference clock. It should be noted that one-cycle of a reference clock is equivalent to a reciprocal of data-read speed from a disk (data-write speed is equal to data-read speed), a data transfer rate. Data transfer rate is not always constant due to subtle rotation speed fluctuation of a disk, inside/outside perimeter, and the like. Therefore, the delay line of FIG. 17 needs to secure total delay quantity that is same as or larger than one-clock cycle of a reference clock at the time of lowest data transfer rate.
For example, provided that lowest data transfer rate is 10 Mbps, minimum essential delay quantity is 100 ns. On the other hand, provided that delay quantity for one stage of a buffer logic (termed as correction accuracy hereinafter) in the delay line is 0.5 ns, the delay line needs two hundred stages of buffer logics. As correction accuracy is degraded, the delay line needs fewer stages. However, this sacrifices highly accurate phase synchronization in case of high data transfer rate. On the contrary, correction accuracy needs to be enhanced for high data transfer rate. Not to mention, enhancement of correction accuracy means increase of stages for the delay line. However, concerning a case of high data transfer rate, total delay quantity actually required can be achieved with a small number of stages in the delay line. This means the delay line has a large number of unnecessary circuits. As a result, power consumption is more than necessary.
Furthermore, if the number of stages in a delay line is excessively large, the fact itself is problematic. That is, if a circuit has delay lines with a very large number of stages, the circuit contains a significant number and varieties of clock signals that differ in phase within a narrow range. This causes large noises and as secondary phenomena, erroneous operation to circuits around the delay lines, and characteristic deterioration take place.
Furthermore, delay quantities of respective buffer logics that constitute a delay line are not always uniform. As the number of stages is larger, delay quantity variation among buffer logics affects operation of the delay line more seriously. In case variation among buffer logics is large, it is possible that actual delay quantity for a selected delay clock differs from desired delay quantity. Therefore, accurate phase correction cannot be made and frequency of corrections to approximate a desired phase increases. That is, it takes long for phase correction to converge. In case phase correction does not converge within a range of recorded phase correction patterns, a correction must be started from beginning. In such a case, a disk must be rotated many times to continue phase corrections.